Computers have historically been designed to execute instructions sequentially; that is, one after another. While sequential execution of computer instructions does provide a logical and orderly method of operation, the ever-present demand to increase processing speed has led researchers to explore ways of implementing a parallel execution scheme.
There are numerous problems which must be overcome if one is to successfully design a computer or microprocessor which is capable of executing multiple instructions in parallel. For example, microprocessors typically have an instruction set architecture which includes hundreds of individual instructions. Counting all of the different kinds of addressing modes for a given architecture, the total number of possible opcodes is likely to number somewhere in the thousands. Pairing all of the thousands of possible first instructions with all the possible second instructions for a given instruction set could easily result in millions of different combinations. Designing a machine which is capable of executing all of these various combinations is a formidable task. It is appreciated that the design complexity can be so great that such a problem becomes unmanageable. Building several decoders which could decode the complete instruction set in a parallel machine capable of executing instruction pairs without large time delays is problematic.
Another associated problem with building a computer capable of parallel execution of instructions is that it must also be able to run software which is designed for prior art machines; that is, machines which operate by sequential execution of instructions--one instruction per clock cycle. In other words, a parallel machine must give the appearance of sequential operation.
As will be seen, the present invention discloses a computer system capable of executing two instructions in a single clock cycle. The invention operates by decoding a pair of instructions selected from a given instruction set and then executes them in parallel to get a correct result. One of the salient features of the present invention is that the computer system only issues two instructions in parallel if there are no register dependencies between the paired instructions.